The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures that include interconnects and methods for forming a structure that includes interconnects.
An interconnect structure may be used to provide connections with device structures fabricated by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization levels formed using a damascene process in which via openings and trenches are etched in a interlayer dielectric layer and filled with metal to create vias and lines of the different metallization levels. The interlayer dielectric layer may be formed from low-k dielectric materials that provide a reduced capacitance.
Further reductions in capacitance may be achieved through the use of airgaps, which have a minimum achievable permittivity. The airgaps are formed after the lines of the metallization level are formed in the interlayer dielectric layer. An etching process is used to remove the interlayer dielectric layer between the lines and define cavities in regions where airgaps are desired. A conformal dielectric layer is deposited that coats the surfaces surrounding the cavities and pinches off at the cavity entrances to surround and encapsulate the airgaps. The etching process may damage the metal forming the lines, especially if an over-etch is required to remove the interlayer dielectric layer. For example, the etching process may erode and bevel or round the corners of the lines. The loss of the metal at the corners of the lines results in an increased resistance, which degrades performance and at least in part defeats the purpose underlying the introduction of airgaps to reduce the capacitance.
Improved structures that include interconnects and methods for forming a structure that includes interconnects are needed.